FIG. 9 shows one example of a multi-channel A/D conversion device, which is so configured that a voltage of each input terminal 2 is selected by an analog multiplexer 1 and the selected input voltage is given to an A/D converter 4 through a common line 3. A parasitic capacitor Cf generally exists in the analog multiplexer 1 as shown by a broken line in the figure. As a result, the input voltage of the channel selected last time remains in the parasitic capacitor Cf, and an A/D conversion error arises due to its effect. Therefore, the input part of each channel is equipped with a buffer amplifier 5.
In the A/D conversion device shown in FIG. 9, a conversion reference voltage Vref of the A/D converter 4 is often set equal to the power supply voltage Vdd. In this case, when the voltage of the input terminal 2 becomes close to either Vdd that is the full scale or 0 V that is a zero point, an offset voltage increases because of a characteristic of the buffer amplifier 5, which produces an A/D conversion error. Moreover, if the voltage of the input terminal 2 exceeds the power supply voltage Vdd or falls below 0 V due to floating ground potential etc., it is impossible to obtain an A/D converted value corresponding to the input voltage.
On the other hand, FIG. 10 shows the configuration of a multi-channel A/D conversion device disclosed in JP 2001-111424A. In this device, the common line 3 is configured to be connectable to the ground line through a switching circuit 6. That is, the A/D conversion device is so configured that the influence of the residual voltage in the capacitor Cf is eliminated by turning on the switching circuit 6 and initializing the common line 3 to discharge the stored charge of the parasitic capacitor Cf.
However, the parasitic capacitor Cf of the analog multiplexer 1 still exists. As a result, a current flows from the input terminal 2 of the selected channel into the parasitic capacitor Cf, which is now at the ground potential, producing an error arising from delay in stabilizing the voltage of the common line 3. Therefore, it is necessary to connect a capacitor C1 having a capacitance sufficiently large to the parasitic capacitor Cf externally to each input terminal 2. This capacitor C1 with a resistor R1 also functions as a filter circuit 7.
In addition, the necessity of setting the electrostatic capacity of the capacitor C1 constituting the filter circuit 7 to a large value will add cost of the filter circuit 7 that is an external part. Further, an area for its installation on a substrate will be enlarged.
JP 2001-223586A discloses another multi-channel A/D conversion device equipped with a holding capacitor in front of an A/D converter. This holding capacitor is charged up to a reference voltage that is set to an intermediate level in the possible voltage range of an analog signal before a sampling circuit starts sampling.
Further, JP 2003-031415A discloses a still another A/D conversion device. In this device, first and second level shift circuits take in terminal voltages of the high and low voltage sides of a current detection resistor, respectively, and output voltages higher than the input voltage by fixed voltages, respectively. The difference of A/D converted values provided by passing them through the respective level shift circuits is detected as a current value. This detected value is corrected.